To provide a switched capacitor charge redistribution sequential approximation type analog-to-digital converter which neither greatly increases in circuit scale nor increases conversion time while its quantization error is uniformly distributed between +0.5LSB and -0.5LSB.

Disclosed is an improved binary weighted switched capacitor charge redistribution sequential approximation type analog-to-digital converter (ADC), which is equipped with a mechanism for adding electric charges corresponding to the least significant digit bit (LSB) of the ADC to electric charges accumulated in a switched capacitor after the sampling stage of the ADC, thereby providing the quantization error which is uniformly distributed between +0.5LSB and -0.5LSB without requiring any additional processing clock cycle.