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Title:
CHARGING AND DISCHARGING CIRCUIT
Document Type and Number:
Japanese Patent JP2006080836
Kind Code:
A
Abstract:

To provide a charging and discharging circuit which reduces an influence given by a parasitic capacity.

The charging and discharging circuit which performs charging and discharging in a capacity element includes a current mirror circuit having a first transistor and a second transistor which are connected by a diode, a first current source which supplies a first current to the first transistor, a second current source which supplies a second current to the second transistor, a third transistor which is provided at the ground side of the first transistor and makes the current path of the first transistor turn on regularly, and a fourth transistor which is provided at the ground side of the second transistor and makes the current path of the second transistor turn on or interrupt. The conduction or non-conduction state of the fourth transistor is changed. Consequently, charging and discharging according to the third current and the second current flowing to the second transistor generated according to the first current are performed to the capacity element connected to the connection point of the second current source and the second transistor by switching the conduction or non-conduction state of the fourth transistor.


Inventors:
FUKUSHI IWAO
OKADA NORIAKI
Application Number:
JP2004262087A
Publication Date:
March 23, 2006
Filing Date:
September 09, 2004
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H03K4/06; H03K4/56
Attorney, Agent or Firm:
Isshiki International Patent Service Corporation



 
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