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Title:
CIRCUIT INPUT AND CIRCUIT STATE EVALUATION METHOD AND EVALUATION DEVICE
Document Type and Number:
Japanese Patent JP2010140385
Kind Code:
A
Abstract:

To provide a circuit input and circuit state evaluation method and evaluation device, allowing quantitative and detailed evaluation of relation between circuit input and a circuit state.

The circuit input and circuit state evaluation method includes: an input step (S01) of applying an input voltage to an input terminal 10 of a transistor circuit 2; a calculation step (S02) of calculating an operation state of each MOS (Metal Oxide Semiconductor) transistor M11, M12, M21, M22 based on an output voltage (an output signal) from each MOS transistor M11, M12, M21, M22; a display step (S03) of continuously displaying the operation states calculated according to an application time or a change amount of the input voltage; a selection step (S04) of selecting at least a part of the operation state from the operation states displayed for detailed evaluation according to a prescribed algorithm; and a generation step (S05) of generating a new input signal changing the selected operation state.

COPYRIGHT: (C)2010,JPO&INPIT


Inventors:
MIURA YUKIYA
Application Number:
JP2008317927A
Publication Date:
June 24, 2010
Filing Date:
December 15, 2008
Export Citation:
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Assignee:
UNIV TOKYO METROPOLITAN
International Classes:
G06F17/50; G01R31/28; G01R31/3183
Domestic Patent References:
JP2007521475A2007-08-02
JP2004213267A2004-07-29
JP2007521475A2007-08-02
JP2004213267A2004-07-29
Foreign References:
Other References:
JPN6012051601; Yukiya Miura et al.: 'Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study' Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , 20031103, p.279-286
JPN6012051601; Yukiya Miura et al.: 'Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study' Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , 20031103, p.279-286
Attorney, Agent or Firm:
深澤 潔