To provide a circuit input and circuit state evaluation method and evaluation device, allowing quantitative and detailed evaluation of relation between circuit input and a circuit state.
The circuit input and circuit state evaluation method includes: an input step (S01) of applying an input voltage to an input terminal 10 of a transistor circuit 2; a calculation step (S02) of calculating an operation state of each MOS (Metal Oxide Semiconductor) transistor M11, M12, M21, M22 based on an output voltage (an output signal) from each MOS transistor M11, M12, M21, M22; a display step (S03) of continuously displaying the operation states calculated according to an application time or a change amount of the input voltage; a selection step (S04) of selecting at least a part of the operation state from the operation states displayed for detailed evaluation according to a prescribed algorithm; and a generation step (S05) of generating a new input signal changing the selected operation state.
COPYRIGHT: (C)2010,JPO&INPIT
| JP2007521475A | 2007-08-02 | |||
| JP2004213267A | 2004-07-29 | |||
| JP2007521475A | 2007-08-02 | |||
| JP2004213267A | 2004-07-29 |
JPN6012051601; Ｙｕｋｉｙａ Ｍｉｕｒａ ｅｔ ａｌ．: 'Ａｎａｌｙｓｉｓ ａｎｄ Ｔｅｓｔｉｎｇ ｏｆ Ａｎａｌｏｇ ａｎｄ Ｍｉｘｅｄ-Ｓｉｇｎａｌ Ｃｉｒｃｕｉｔｓ ｂｙ ａｎ Ｏｐｅｒａｔｉｏｎ-Ｒｅｇｉｏｎ Ｍｏｄｅｌ： Ａ Ｃａｓｅ Ｓｔｕｄｙ' Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅ １８ｔｈ ＩＥＥＥ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓｙｍｐｏｓｉｕｍ ｏｎ Ｄｅｆｅｃｔ ａｎｄ Ｆａｕｌｔ Ｔｏｌｅｒａｎｃｅ ｉｎ ＶＬＳＩ Ｓｙｓｔｅｍｓ , 20031103, ｐ．２７９-２８６