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Patent Searching and Data


Title:
CIRCUIT SIMULATION SYSTEM
Document Type and Number:
Japanese Patent JPS634345
Kind Code:
A
Abstract:

PURPOSE: To shorten the time of network simulation by making a selection so that the value of a virtual capacitor interposed in a linearization network is a value where iterative calculation by a relaxing method converges on.

CONSTITUTION: The node equation of a DC analysis of a nonlinear resistance network with the number N of nodes is represented as F(V)=Y.V-J(V)=0. This is solved by the iterative equation VK+1=VK-Ja-1F(VK) of an NR (Newton- Raphson) method. For the purpose of the calculation based upon this iterative equation, a virtual capacitor is interposed between each node and the ground and the state equation of a virtual linear network which has a Jacobian matrix Ja as a conductance matrix is generated. This state equation is integrated numerically by a BE (backward Euler) method. At this time, a linear equation is obtained in each time step, so this is calculated with the iterative equation of a GS (Gauss-Seidel) method.


Inventors:
TANAKA MAMORU
ASAI MITSUO
Application Number:
JP14865886A
Publication Date:
January 09, 1988
Filing Date:
June 25, 1986
Export Citation:
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Assignee:
TANAKA MAMORU
International Classes:
H03K19/00; G06F11/26; G06F17/50; G06F19/00; (IPC1-7): G06F11/26; G06F15/20; G06F15/60; H03K19/00
Attorney, Agent or Firm:
Yoshiyuki Osuga