Title:
クロック周波数の制御方法および電子機器
Document Type and Number:
Japanese Patent JP3742364
Kind Code:
B2
Abstract:
An electronic apparatus includes a clock oscillator (3) for supplying a clock signal, a processor (2) for generating an internal clock on the basis of the clock signal supplied from the clock oscillator (3), and a control unit (14) for controlling a frequency of the internal clock in accordance with a ratio of an executable instruction count per unit time to a clock count per unit time of the internal clock generated by the processor (2).
More Like This:
JP2000250666 | CENTRAL PROCESSOR AND METHOD FOR REDUCING POWER CONSUMPTION OF ITS CENTRAL PROCESSOR |
JP2003330567 | COMPUTER SYSTEM |
JPH11284437 | OSCILLATOR CIRCUIT |
Inventors:
Michio Yamashita
Katsuki Uedoko
Katsuki Uedoko
Application Number:
JP2002190890A
Publication Date:
February 01, 2006
Filing Date:
June 28, 2002
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F1/04; G06F1/08; G06F1/32; G06F9/30
Domestic Patent References:
JP11353052A | ||||
JP1292416A | ||||
JP6065350A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai