To provide a clock generation circuit and a display device having the same, wherein a power consumption can be reduced.

The clock generation circuit contains a first voltage generator, a second voltage generator, and an intermediate voltage generator. The first voltage generator outputs a first voltage during a high section, and the second voltage generator outputs a second voltage lower than the first voltage during a low section. The intermediate voltage generator outputs one or more intermediate voltages which have a voltage level between the first voltage and the second voltage, between a first transition section transiting from the high section to the low section and a second transition section transiting from the low section to the high section. Accordingly, the power consumption of the display device having the clock generation circuit can be reduced.