To provide a clock generation circuit with a small circuit scale, which generates, when the discretely set highest operation frequency of a circuit to be controlled is not a natural number multiple of the frequency of a reference clock, a clock of a frequency not exceeding the highest operation frequency and close to the highest operation frequency by use of the reference clock.

The clock generation circuit comprises a first frequency divider 6 for inputting a first clock CLK1 of 27 MHz and dividing the frequency of the first clock CLK1 to 1/2k times (k is a natural number of 2 or more) to generate a second clock CLK2; and a multiplier 7 for inputting the second clock CLK 2 from the first frequency divider 6 and multiplying the frequency of the second clock CLK 2 m-times (m is a natural number of 2 or more) to generate a third clock CLK 3.