Title:
CMOS OUTPUT CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND MOBILE BODY
Document Type and Number:
Japanese Patent JP2021166240
Kind Code:
A
Abstract:
To provide a CMOS output circuit with reduced size in which the occurrence of a latch-up phenomenon in a CMOS circuit can be suppressed regardless of the polarity of abnormal voltage, a semiconductor device including the CMOS output circuit, and an electronic apparatus and a mobile body including the semiconductor device.SOLUTION: A CMOS output circuit includes a CMOS circuit that includes a first PMOS transistor and a first NMOS transistor, a first switching circuit that controls the potential of a substrate of the first PMOS transistor, and a second switching circuit that controls the potential of a substrate of the first NMOS transistor. The first switching circuit includes a second PMOS transistor and a third PMOS transistor. The second switching circuit includes a second NMOS transistor and a third NMOS transistor.SELECTED DRAWING: Figure 2
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Inventors:
IKEDA MASUHIDE
Application Number:
JP2020068854A
Publication Date:
October 14, 2021
Filing Date:
April 07, 2020
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/822; H01L21/8238; H01L27/04; H01L27/092
Attorney, Agent or Firm:
Kazuaki Watanabe
Satoshi Nakai
Hiroki Matsuoka
Satoshi Nakai
Hiroki Matsuoka