COMPOUND SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF AND WAFER

Title:

COMPOUND SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF AND WAFER

Document Type and Number:

Japanese Patent JPS63305567

Kind Code:

A

Abstract:

PURPOSE: To obtain a short-gate GaAs.MES.FET suitable for rapid operation and high.frequency operation, by forming a non-active region apart from an active region such that the non-active region defines Schottky junction with a metal forming a gate electrode.

CONSTITUTION: A gate electrode 7 is extended into a non-active region 11 through an active region 10 in order to provide a bonding pad 15 to which wire 14 is bonded. A wide bonding pad 15 is provided in the non-active region 11. An interconnecting layer 12 is contacted with the surface of an n-type channel layer 2 by Schottky junction in the active region 10, while it is also contacted with a semi-insulating layer 13 by Schottky junction in the non-active region 11. Accordingly, stable characteristics can be obtained since no current leakage is caused between the interconnecting layer 12 and the semi-insulating layer 13. Thus, it is made possible to provide a short-gate GaAs.MES.FET suitable for rapid operation and high-frequency operation.

Inventors:

SHIMIZU SHUICHI
SAIGO MASAKO

Application Number:

JP14112287A

Publication Date:

December 13, 1988

Filing Date:

June 05, 1987

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

H01L29/04; H01L21/20; H01L21/338; H01L29/80; H01L29/812; (IPC1-7): H01L21/20; H01L29/04; H01L29/80

Attorney, Agent or Firm:

Satoru Akita (1 person outside)

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