PURPOSE: To reduce an inspecting time to a semiconductor memory device and to improve inspection efficiency by screening to a redundant cell array, as well before storing the address of a defective memory cell.

CONSTITUTION: This device is provided with the redundant memory cell arrays 2a, 2b compensating the defective memory cell of a normal memory cell array 1 and simultaneously a defective address storing parts 7R, 7C storing the address of detective memory cell and an address comparator circuits 5R, 5C comparing the storing content and an address signal. The outputs of these circuits 5R, 5C are inputted to the decoder of the redundant memory cell array or the normal memory cell array 1. Then, activating circuits 21R, 21C making forcedly output signals REr, REc output from the address comparator circuits 5R, 5C based on the input of external signals Er, Ec are provided. Thus, the redundant memory arrays 2a, 2b, as well are screened.