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Patent Searching and Data


Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPS6275822
Kind Code:
A
Abstract:

PURPOSE: To reduce the load of a programmer by providing a clock selecting circuit and a clock switching program and giving the dynamic change to the clock speed at the part of a software timer.

CONSTITUTION: Both clocks A and B are supplied to a clock selecting circuit 1 via lines 2 and 3 respectively and either one of both clocks is usually delivered through a line 5. When the input clock is changed, the control signal SEL of a line 4 is allocated to a certain port address. Then an access is given to the relevant port by a program and the signal SEL is inverted. In other words, the count frequency is set at a part equivalent to a timer (loop) by a prepared program and an access is given to the port to which the circuit 1 is allocated. Then this port is switched as necessary to the logic clock obtained when the program is designed. Thus the clocks are fixed during an actual loop and the replacement of programs is omitted. As a result, the load of a programmer is reduced.


Inventors:
KONNO TOSHIKAZU
Application Number:
JP1985000216474
Publication Date:
April 07, 1987
Filing Date:
September 30, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F1/08; G06F1/04; G06F1/14; (IPC1-7): G06F1/04
Domestic Patent References:
JPS6020224A1985-02-01
JPS61109126A1986-05-27