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Title:
DATA PROCESSOR OF MICROPROGRAM CONTROL
Document Type and Number:
Japanese Patent JPS5543635
Kind Code:
A
Abstract:

PURPOSE: To realize a high-speed process with a short length of the microorder word by starting the fetch control for the macroorder at the wake-up caused by the microorder and giving the random logic control thereafter based on no microorder.

CONSTITUTION: The microprogram order indicating the start of the microorder fetch is detected through the specific pattern detection circuit. Based on the output of the detection circuit, macroorder fetch procedure control means 100 is started. Then the microprogram head address is produced through selection control means 104 for execution of the macroorder based on the decoding result of macroorder decoder circuit 103, thus carrying out the macroorder fetch. After the fetch end is detected by fetch end detection means 101, the output of means 104 is utilized.


Inventors:
MAEJIMA HIDEO
Application Number:
JP1978000115925
Publication Date:
March 27, 1980
Filing Date:
September 22, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F9/26; G06F9/22; (IPC1-7): G06F9/22



 
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