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Patent Searching and Data


Title:
DATA RECEIVER AND ADAPTIVE EQUALIZER CIRCUIT
Document Type and Number:
Japanese Patent JP2011259460
Kind Code:
A
Abstract:

To provide a data receiver and an adaptive equalizer circuit that can suppress a circuit size and reduce power consumption.

A plurality of receiving circuits 2a to 2d are connected to transmission lines and receive data signals from the transmission lines. The receiving circuits 2a to 2d include an equalizer for shaping a waveform of the received data signal. An adaptive equalizer circuit 3 is provided with every one for all or, two or more predetermined number of the plurality of receiving circuits 2a to 2d. The adaptive equalizer circuit 3 calculates equalization coefficients for shaping the waveform of the equalizers of the corresponding receiving circuits 2a to 2d and outputs the equalization coefficients to the corresponding receiving circuits 2a to 2d.


Inventors:
YAMAGUCHI HISAKATSU
Application Number:
JP2011156582A
Publication Date:
December 22, 2011
Filing Date:
July 15, 2011
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B3/04; H03H21/00; H04L25/03
Domestic Patent References:
JPH01251811A1989-10-06
JPH10308784A1998-11-17
JPH1075237A1998-03-17
JPH09233007A1997-09-05
JPH01123535A1989-05-16
JPH0865222A1996-03-08
JP2003223761A2003-08-08
JP2005332453A2005-12-02
Foreign References:
WO2005013505A12005-02-10
Attorney, Agent or Firm:
Takeshi Hattori