To achieve data save processing appropriately even in an environment with a severe time restriction such as a response time.

A data save unit 3, which is a digital circuit for processing a data read request or write request to be transmitted from a CPU 2 to a first memory area 4, reads data from a storage device inside the data save unit 3 or the first memory area 4 and transmits the data to the CPU 2, when the CPU 2 requires to read data. In addition, when the CPU 2 requires to write data, the data save unit 3 stores a write destination address and write data as a set of entries in the inner storage device once, reads the entries, one set at a time, while the CPU 2 requires neither to read nor to write data, saves the data from the first memory area 4 to a second memory area 5, and then writes new data in the first memory area 4.