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Patent Searching and Data


Title:
DATA TROUBLE DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6234436
Kind Code:
A
Abstract:

PURPOSE: To reduce the quantity of the hardware used in a data trouble detecting circuit so as to make maintenance of the circuit easier, by making the selecting designation of a selector the same as parity rule designating information.

CONSTITUTION: Usually, command from a parity rule designating information line 70 is an odd parity rule and a 2-1 selector 9 selects an OR circuit 8a. If a trouble occurs on at least one side of memory circuits 41 and 42 under this condition, the output of the OR circuit 8a becomes to have a logic '1' and trouble information is outputted to the check result outputting information line 60 of the 2-1 selector 9. When the information from the information line 70 is changed to an even parity rule, the selector 9 selects an AND circuit 8b. The output of the AND circuit 8b becomes to have a logic '1' only when the trouble information is outputted to both check result outputting information lines 61 and 62 and trouble information indicating that normality of parity generating circuits 21 and 22 and parity checking circuits 51 and 52 is confirmed is outputted to the check result outputting information line 60 of the 2-1 selector 9.


Inventors:
ONO CHUKICHI
KOGURE KOJI
KURODA KIYOHIKO
Application Number:
JP17344385A
Publication Date:
February 14, 1987
Filing Date:
August 06, 1985
Export Citation:
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Assignee:
NEC CORP
NIPPON TELEGRAPH & TELEPHONE
FUJITSU LTD
International Classes:
H04L1/00; (IPC1-7): H04L1/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)