To output each data by inputting directly the video stream of the MPEG2 system, a program stream and a transport stream to the decoder.

A serial interface signal of compression video data by n-channels inputted to an input terminal 1 is converted into parallel compression video data by an S/P conversion circuit 21, decoded by a decoder 22 and the information of header data is fed to a control circuit 5. Compressed video data are fed to video decoders 411-41n via reception buffers 31-3n for each channel under the control of the control circuit 5 and decoded. Furthermore, changeover switches 431-43n are switched to output video signals from the video decoders 411-41n or delay memories 421-42n to a channel changeover device 6 and a video image is outputted to a monitor 7.