Title:
DEMODULATOR
Document Type and Number:
Japanese Patent JPH02305151
Kind Code:
A
Abstract:
PURPOSE: To minimize the harmonic distortion by dividing a filtered product by a function of a filtered square to generate a demodulation output sample. CONSTITUTION: Multipliers 26, 24 and 22 generate products S0 <2> , S0 S1 , and S1 <2> respectively, and the value S0 S1 from a data latch 30 is connected to a divided input connection line of a divider 40 through a low pass filter 34, and values S1 <2> and S0 <2> are alternately connected to a divider input connection line of the divider 40 through a multiplexer 36 and a low pass filter 38. The multiplexer 36 connects the value S0 <2> to the divider 40 during a period t3 and connects the value S1 <2> to the divider 40 during a period t4 . During the period t3 , the divider 40 generates a quotient (S0 S1 /S0 <2> )LP to be inputted to a data latch 44 in response to a signal P1 ; and during the period t4 , the multiplexer 36 generates a quotient (S0 S1 /S1 <2> )LP to be inputted to a data latch 42 in response to a signal P2 . Values in latches 42 and 44 are supplied to input terminals of an adder 46 which generates the sum of S0 S1 /S1 <2> +S0 S1 /S1 <2> during a period t5 . Thus, the harmonic distortion is prevented.
Inventors:
TAKAHASHI MINORU
Application Number:
JP11190590A
Publication Date:
December 18, 1990
Filing Date:
May 01, 1990
Export Citation:
Assignee:
RCA LICENSING CORP
International Classes:
H04L27/14; B60G5/04; B62D13/02; H03D3/00; (IPC1-7): H04L27/14
Attorney, Agent or Firm:
Katsunori Watanabe