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Title:
DIGITAL MULTIPLE CONVERSION SYSTEM
Document Type and Number:
Japanese Patent JPS54114030
Kind Code:
A
Abstract:

PURPOSE: To secure the direct connection of the multiplied signal to the transmission line with no limitation given to the information speed of the multiplied digital signal but giving the word multiplication within one frame to the signal featuring the bit speed of integer-times as high as the frame repetitive frequency.

CONSTITUTION: The diagram shows the signal arrangement within a frame for the multiplied signal featuring the frame repetitive frequency of 8K Hz and 1.544Mb/S, that is, the signals are arranged with r×8Kb/s of the multiplied digital signal speed and in continuous r bits and thus word-multiplied. For instance, an optional bit position which continues bt 3 bits is allotted to the signal of 24Kb/s. In this case, not limitation is given at all to the order of arrangement of the multiplied signals. If a simple limitation is given to the arrangement order of the multiplied signals, no zero continuation of more than 7 bits is caused and thus the multiplied signal featuring the mark rate of more than 1/8 can be obtained. Thus, the direct continuation becomes possible for the multiplyed signals at the transmission line of the existing PCM-24B system or the like.


Inventors:
OKIMI KATSUYA
WASHIYAMA IKUO
Application Number:
JP1978000021122
Publication Date:
September 05, 1979
Filing Date:
February 25, 1978
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04J3/06; H04J3/16; (IPC1-7): H04J3/00
Domestic Patent References:
JPS5141914A1976-04-08



 
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