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Patent Searching and Data


Title:
DYNAMIC FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH0548434
Kind Code:
A
Abstract:

PURPOSE: To increase the operating speed sufficiently by controlling a power supply current of a differential amplifier circuit with a clock signal in place of controlling the differential amplifier circuit with a transfer gate.

CONSTITUTION: When a clock CK goes to a high level, a transistor(TR) 33 acts like a current source, an input signal D of a differential amplifier circuit 30a of a master circuit 30 is inversely amplified and outputted to an output terminal Q of the master circuit 30. In this case, a data signal is not propagated but latched in a slave circuit 40. When the clock signal CK goes to a low level, a complementary signal of the clock signal CK goes to a high level, the data signal is inversely amplified by a differential amplifier circuit 40a of the slave circuit 40 and outputted to an output terminal Q of the slave circuit 40. In this case, the data signal is not propagated but latched in the slave circuit 40. Thus, the circuit speed is quickened by a delay time due to a transfer gate.


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Inventors:
MURATA KOICHI
TOGASHI MINORU
OHATA MASANOBU
SUZUKI MASAO
Application Number:
JP1991000228743
Publication Date:
February 26, 1993
Filing Date:
August 14, 1991
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
川久保 新一