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Title:
ERROR CORRECTION APPARATUS AND ERROR CORRECTION METHOD
Document Type and Number:
Japanese Patent JP3734486
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To obtain an error correction apparatus having high error correction capability by generating a highly accurate erasure flag.
SOLUTION: The error correction apparatus is provided with an error correction means 4 for applying an error correction processing to one of a plurality of input signals to output a first error position signal corresponding to a position of error data in the one input signal and a first signal corresponding to the result of the error correction processing, and an error position signal generating means 5 for outputting a second error position signal corresponding to a position of error data in the other input signals based upon the first error position signal outputted from the error correcting means 4, and on the basis of the second error position signal, the error correction means 4 applies the error correction processing to the other input signals to output the second signal.


Inventors:
前野 晶子
Application Number:
JP2003000412069
Publication Date:
January 11, 2006
Filing Date:
December 10, 2003
Export Citation:
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Assignee:
三菱電機株式会社
International Classes:
G06F11/10; H03M13/29; H03M13/37; H04L1/00; (IPC1-7): H03M13/29; G06F11/10; H03M13/37; H04L1/00
Domestic Patent References:
JP8293802A
JP63020921A
JP7202907A
JP7121998A
Foreign References:
WO2001047125A1
Attorney, Agent or Firm:
前田 実
山形 洋一



 
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