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Patent Searching and Data


Title:
ERROR COUNT CIRCUIT
Document Type and Number:
Japanese Patent JPH07177130
Kind Code:
A
Abstract:

PURPOSE: To prevent mis-count on the occurrence of the fault of a power supply by allowing an error counter to stop its operation when a power supply supervisory section provided to an external device connected to an optical transmission line receives a disable signal.

CONSTITUTION: In the error count circuit in which an error counter 11 inputting the number of code errors of a main signal in an optical transmission terminal station equipment (external device) 2 connected to an optical transmission line as a high speed error pulse counts the error pulse based on a clock signal sent from an oscillator 14 for each prescribed time and the error count for each prescribed time is outputted, a power supply supervisory section 22 of an optical transmission terminal station equipment 2 supervises its power supply voltage to detect a voltage drop and interruption of power. Then the power supply supervisory section 22 gives an enable signal or a disable signal as a control signal CS to a terminal of the error counter 11 and the count operation of the error counter 11 is stopped when the disable signal is given, Thus, the operation of the error counter 11 is inhibited before a noise or the like is inputted.


Inventors:
FUKUMITSU KATSUMI
TAKADA TADAYUKI
Application Number:
JP1993000321468
Publication Date:
July 14, 1995
Filing Date:
December 21, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B10/556; H04B10/03; H04B10/07; H04L1/00; H04L1/24; (IPC1-7): H04L1/00; H04B10/00
Attorney, Agent or Firm:
茂泉 修司