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Title:
FIELD PROGRAMMABLE GATE ARRAY AND ELECTRONIC APPARATUS
Document Type and Number:
Japanese Patent JP2015201814
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To quickly restore a system constituted by a logic circuit of an FPGA.SOLUTION: A field programmable gate array including a programmable logic circuit comprises: a configuration memory to which the logic circuit is set; and a countermeasure circuit for normalizing the configuration memory when the configuration memory includes a software error. A redundant configuration is assembled by an active system circuit and standby system circuit constituted by the field programmable gate array. The countermeasure circuit, at the time of detecting a software error generated in the configuration memory constituting the active system circuit, switches the active system circuit and standby system circuit; executes error correction for recovering from a secondary failure caused by the detected software error; and restores a value held in the logic circuit after the error correction.

Inventors:
TAMURA YUKIHISA
MAKINO MANABU
YASUI CHIHARU
SHINPO KENICHI
SHIBAZAKI MASATOSHI
KUSANO YOSHIMASA
Application Number:
JP2014080985A
Publication Date:
November 12, 2015
Filing Date:
April 10, 2014
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/177; G06F11/20
Domestic Patent References:
JP2006053873A2006-02-23
JP2012053778A2012-03-15
JP2009017010A2009-01-22
JP2006262227A2006-09-28
JP2010134678A2010-06-17
JP2013187699A2013-09-19
Foreign References:
US20070283193A12007-12-06
Attorney, Agent or Firm:
Fujio Patent Office