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Title:
FIELD PROGRAMMABLE GATE ARRAY
Document Type and Number:
Japanese Patent JP2015201813
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To normalize a function of a logic circuit.SOLUTION: A field programmable gate array including a programmable logic circuit comprises: a configuration memory to which the logic circuit is set; and a countermeasure circuit for normalizing the configuration memory when the configuration memory includes a software error. The countermeasure circuit executes error correction for recovering from a secondary failure caused by the software error generated in the configuration memory; and restores a value held in the logic circuit after the error correction.

Inventors:
MAKINO MANABU
YASUI CHIHARU
TAMURA YUKIHISA
SHINPO KENICHI
TOBA TADANOBU
Application Number:
JP2014080980A
Publication Date:
November 12, 2015
Filing Date:
April 10, 2014
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/177
Domestic Patent References:
JP2013046181A2013-03-04
JP2011216020A2011-10-27
JP2002252558A2002-09-06
JP2007293856A2007-11-08
JP2012053778A2012-03-15
JP2006344223A2006-12-21
Attorney, Agent or Firm:
Fujio Patent Office