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Title:
FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JPS62258514
Kind Code:
A
Abstract:

PURPOSE: To reduce the delay time until a data is outputted after a clock pulse is changed by outputting an input data immediately when the clock is changed to the 2nd output terminal.

CONSTITUTION: When the clock pulse K inputted from a clock pulse input terminal 12 is changed to a high level, the data D inputted from a data input terminal 11 is outputted directly to a data output terminal Q2 provided to the outside of a D latch circuit FF via an N-channel MOSFETq2 turned on by the clock pulse CK of a high level. On the other hand, the input data D is fed alto to the latch circuit FF and latched at the output terminal Q2 of the latch circuit FF.


Inventors:
KAWASHIMA MASATOSHI
Application Number:
JP1985000282888
Publication Date:
November 11, 1987
Filing Date:
December 18, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K3/037; H03K3/356; (IPC1-7): H03K3/037



 
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