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Title:
FORMATION OF SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JPH05160255
Kind Code:
A
Abstract:

PURPOSE: To minimize recombination leak current generated at the isolation boundary caused by ion plantation in a p-n junction in order to prevent the deterioration of characteristics such as amplification factor at the time of manufacturing a heterojunction BT element and permit high-resistance and stable deep isolation.

CONSTITUTION: In an area which is not covered by resist on a multilayer semiconductor epitaxial film which has the p-n junction of a p+-AlGaAs layer 2 and an n-AlGaAs layer 3 on a GaAs substrate 1, an Ar ion which is heavier than oxygen is implanted by the energy which permits the p-n junction to be at a depth between an ion projection range Rp and Rp+δRp and as a result of forming the Ar ion implanting part 6, a p-n junction active area 7 is separated. After annealing is performed in a annealing furnace 8 under the prescribed conditions, an O ion is implanted in the multilayer semiconductor film using a resist pattern as a mask, an O ion implanting part which reaches the substrate 1 is formed and an element area is separated. Annealing is performed again in the furnace 8, a p+ layer is exposed by mesa-etching, (n) and (p) electrodes are formed and an element is annealed to be completed.


Inventors:
WATANABE KAZUO
YAMAZAKI HAJIME
Application Number:
JP35036891A
Publication Date:
June 25, 1993
Filing Date:
December 09, 1991
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L21/265; H01L21/331; H01L21/76; H01L29/205; H01L29/73; H01L29/737; (IPC1-7): H01L21/265; H01L21/331; H01L21/76; H01L29/205; H01L29/73
Attorney, Agent or Firm:
Kugoro Tamamushi



 
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