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Title:
FORMING METHOD FOR INSULATING LAYER AND CONNECTION HOLE, FORMING METHOD FOR WIRING STRUCTURE, AND PATTERN MATERIAL USED TO IMPLEMENT THE SAME METHODS AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2002033562
Kind Code:
A
Abstract:

To provide an insulating layer and via hole forming method which makes the top surface of an insulating layer smooth when the insulating layer and a via hole are formed on a core substrate, can form a thin-film element etc., in good yield with good reliability and a high degree of freedom, and enables fine via-hole formation, a forming method for a wiring structure, and to provide a pattern material used to implement those methods and its manufacturing method.

A liquid insulating layer material 3 is applied over the surface including an electrode 2 on the substrate 1, and projections 22 formed on the pattern material 21 are pressed against the material 3 from above. After the insulating layer 3 is cured while the projections 22 are made to abut against the electrode 2, the pattern material 21 is peeled off. Consequently, via holes 23 can be formed in the insulating layer 3 at the parts of the projections 22. For the purpose, the surface of the pattern material 21 except the projections 22 are formed smoothly and the projections 22 are formed in a desired shape to desired size to form the insulating layer 3 having the smooth surface and desired via holes 23, so that a reliable product can be manufactured in good yield by forming a thin-film element, etc., by using the method.


Inventors:
OGAWA TAKESHI
Application Number:
JP2000218197A
Publication Date:
January 31, 2002
Filing Date:
July 19, 2000
Export Citation:
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Assignee:
SONY CORP
International Classes:
B29C33/40; B29C39/10; B29C39/26; H05K3/00; H05K3/40; H05K3/46; (IPC1-7): H05K3/00; B29C33/40; B29C39/10; B29C39/26; H05K3/40; H05K3/46
Attorney, Agent or Firm:
Hiroshi Osaka