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Title:
FOUR-PHASE PSK SYNCHRONOUS DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6091749
Kind Code:
A
Abstract:

PURPOSE: To suppress crosstalk between channels as less as possible by multiplying codes of an in-phase channel detection output and an orthogonal channel detection output and detecting an inter-channel crosstalk from the difference of the absolute values of the peak values to control a voltage controlled delay device.

CONSTITUTION: A sign discriminator 17 discriminates a sign of an orthogonal channel detection output 14, and when the sign is positive, the discriminator 17 outputs a positive prescribed voltage and when negative, the discriminator 17 outputs a negative prescribed voltage. The output signal 18 and the in-phase channel detection output 13 are inputted to a multiplier 19, where they are multiplied to obtain an output signal 20 where the absolute values of the positive and negative peak values are equal when no inter-channel crosstalk exits and the absolute values are different when the inter-channel crosstalk exits because of the shifted phase of regenerated carriers 7, 8. Then the positive and negative peak values of the output signal 20 are detected by peak detection circuits 21, 22, the outputs are added by an adder 23 and the phase shift of the regenerated carriers is corrected by controlling the amount of delay of the voltage controlled variable delay device 24 with the detection signal.


Inventors:
AMADA NOBUTAKA
SHIBUYA TOSHIFUMI
HORIKOSHI TATSUO
Application Number:
JP19898583A
Publication Date:
May 23, 1985
Filing Date:
October 26, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04L27/22; H04L27/227; (IPC1-7): H04L27/22
Attorney, Agent or Firm:
Akio Takahashi