PURPOSE: To provide the frequency divider circuit applying (2n+1)/2 to a frequency of a master clock with respect to the frequency divider circuit generating a clock resulting from frequency-dividing the frequency of the master clock.

CONSTITUTION: The frequency divider circuit frequency-dividing a master clock 1 whose frequency is N and sending the result as an output clock 6 is provided with a 1/n frequency divider circuit 2 initialized by the output clock and outputting a pulse every time the master clock is counted by (n) (n is an integer being 2 or over), a 1/(n+1) frequency divider circuit 3 initialized by the output clock and outputting a pulse every time the master clock is counted by (n+1), a mask circuit 4 eliminating every other output pulse of the 1/n frequency divider circuit 2 and outputting the result, and a pulse synthesis output circuit 5 receiving an output pulse from the mask circuit 4 and an output pulse from the 1/(n+1) frequency divider circuit 3, synthesizing them and sending the output clock 6 resulting from the frequency of the master clock subjected to (2n+1)/2 frequency division.