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Title:
1/3 FREQUENCY DIVIDING CIRCUIT
Document Type and Number:
Japanese Patent JPH02186718
Kind Code:
A
Abstract:

PURPOSE: To obtain the output of a 1/3 frequency division whose duties of a high level and a low level are equal, by installing plural master slave FF fetching data at the change of rising or falling of a clock, an OR gate and the like.

CONSTITUTION: The non-inverted output Q1 of DFF 5 is connected to the non- inverted input D2 of DFF 6, the inverted output, the inverse of Q1 in DFF 5 to the inverted input, the inverse of D2 in DFF 6, and the OR of the inverted output, the inverse of Q1 in DFF 5 and the inverted output, the inverse of Q2 in DFF 6 is connected to the non-inverted input D1 in DFF 5. The inverted output, the inverse of Q2 of the master slave FF 4 fetching data by the falling change in DFF 6 and the inverted output, the inverse of Q2 in the master slave FF 3 are supplied to the OR gate 8, and the OR is set to be an output signal. Namely, the output of the 1/3 frequency division whose duties of the high level and the low level are equal can be obtained by adding and connecting the gate 8.


Inventors:
NAKAYAMA ISAO
Application Number:
JP632389A
Publication Date:
July 23, 1990
Filing Date:
January 13, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K23/00; H03K23/66; (IPC1-7): H03K23/66
Domestic Patent References:
JPS57133729A1982-08-18
JPS6388919A1988-04-20
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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