PURPOSE: To eliminate the need for complicated timing extraction at an odd number frequency division circuit by providing a counter circuit having a fre quency dividing ratio (n), an exclusive OR gate, an inverter, a D FF and a 1/2 frequency division circuit so as to realize the frequency dividing ratio of (2n-1).

CONSTITUTION: An output of a counter 12 with a time slots 2 and 3 (hereinafter referred to as 'TS') is stored in the D FF 14, inputted to the 1/2 frequency division circuit 15 at the TS 4 to invert the output of the circuit 15, then inputted to the exclusive OR gate 11 to invert the input signal of the circuit 12. At the change point from the TS 3 to the TS 4, the signal input changes from '1' to '0', the output of the gate 11 changes from '1' to '0', the output of the inverter 13 changes from '0' to '1', a Q output of the FF 14 changes from '0' to '1', the output of the circuit 15 changes from '0' to '1', the output of the gate 11 changes from '0' to '1' and the output of the circuit 12 changes from '0' to '1' respectively. The frequency division is realized by operating the circuit 12 within the time of 1/2 period from the TS 3 to the TS 4 with respect to the change point from the TS 2 to the TS 3.