Title:
GENERATING CIRCUIT OF REFERENCE VOLTAGE
Document Type and Number:
Japanese Patent JP3186034
Kind Code:
B2
Abstract:
PURPOSE: To achieve quick rise at the supplying time of power by providing a driving circuit of a reference voltage wiring and a generating source of two reference voltages, and providing the driving circuit with differential amplifiers which control transistors of different current efficiencies and a gate potential.
CONSTITUTION: A driving circuit 2 has two transistors Q1, Q2 to the source of which is applied the power from an external source, differential amplifiers 21, 22 and a resistance R for connecting a common drain of the transistors Q1, Q2 with the ground potential. The differential amplifiers 21, 22 compare the potential of the common drain of the transistors Q1, Q2 with that of a reference voltage generating source 1, thereby to control the gate potential of Q1, Q2. The potential of the common drain of Q1, Q2 is input as a reference voltage to a voltage decreasing circuit 4 through a reference voltage wiring 3. When such power is supplied that makes the current efficiency of Q2 approximately twice the current of the resistance R and the current efficiency of Q1 high, Q1 and Q2 are turned ON. Accordingly, the circuit can rise quickly when the power is supplied, and the reference potential is never changed even when noises are generated in a short cycle.
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Inventors:
Kenji Noda
Application Number:
JP29949191A
Publication Date:
July 11, 2001
Filing Date:
October 21, 1991
Export Citation:
Assignee:
NEC
International Classes:
G05F1/613; G11C11/407; G11C11/413; (IPC1-7): G11C11/413; G05F1/613; G11C11/407
Domestic Patent References:
JP63211414A | ||||
JP270264A | ||||
JP3288218A | ||||
JP2210688A | ||||
JP59135520A | ||||
JP4145509A |
Attorney, Agent or Firm:
Johei Yamashita
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