PURPOSE: To obtain a control logic suited to the parallel transfer of data by producing an AND of the 1st and 2nd signals and latching the AND by a flip- flop at the sampling time.
CONSTITUTION: The conditions obtained by the start 1401 and 1402 of the order (m) preceding the start 1400 of the order (n) are defined as a 2nd signal, and the signal serving as the start timing of the order (m) is defined as a 1st signal. The 1st and 2nd signals are sampled in the start timing (1st time) of the order (m), and an AND 1404 of the 1st and 2nd signals is produced for each condition. The outputs of the ANDs set to the signals of different conditions and orders are sorted by the 1st time. Thus the groups of conditions are generated for each order (m). In this connection, an OR 1406 is produced to the signal of each order and used as the input of a flip-flop 1407. Then the outputs of FFs set to each order (m) are collected for production of an OR 1408. The output of the OR 1408 is used as a start signal of the order (n). Thus the control logic is obtained for control of the parallel data starting actions.
MIURA CHIHEI
SHIMIZU TSUGUO
