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Title:
HARDWARE LOGICAL SIMULATOR
Document Type and Number:
Japanese Patent JPS6426243
Kind Code:
A
Abstract:

PURPOSE: To easily detect the coverage of simulation by writing and reading prescribed data in and out of an address of a storage means determined according to the state of a specified signal group after variation at the time of simulation.

CONSTITUTION: A specifying means 2 which specifies a signal group in a simulation model and an incorporating means 3 which generates a storage means inputting the specified signal group as an address and incorporates it in the model are provided. Further, a writing means 1 which writes the prescribed data in the address of the storage means determined according to the state of the state of the signal group specified by the specifying means 2 after the variation at the end of simulation and a reading means 5 which reads the stored data are provided. The storage data in the storage means are checked after the end of the simulation and its unwritten address shows a combination where simulation is not performed. Consequently, the combination where no simulation is performed is regarded as a target, a repeated test case is eliminated, and efficient simulation for sufficient logical verification becomes possible.


Inventors:
KURASHITA MASAHIRO
NOMIZU NORINAGA
Application Number:
JP1988000034027
Publication Date:
January 27, 1989
Filing Date:
February 18, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F17/50; G06F19/00; (IPC1-7): G06F11/26; G06F15/20



 
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