To provide an IC card processor capable of performing a series of processing alternately to two IC cards and being made compact.
An IC card RW terminal 1 comprises first and second antennas 11, 12, first and second data transmitting circuits 19, 20, a data receiving circuit 21, an antenna switching circuit 26 switching the two antennas 11, 12, a transmission control circuit 22, and a receiving control circuit 23. When a series of processing is alternately performed to the two IC cards, a transmission data signal is transmitted to the IC card 6 for identification from the first antenna 11, and a transmission data signal is transmitted to the IC card 8 for authentication from the second antenna 12. The antenna switching circuit 26 is controlled to use the first antenna 11 when receiving a receive data signal from the IC card 6 for identification and to use the second antenna 12 when receiving a receive data signal from the IC card 8 for authentication.
| JP2002049283A | 2002-02-15 | |||
| JP2005348241A | 2005-12-15 | |||
| JP2005259071A | 2005-09-22 | |||
| JP2005117460A | 2005-04-28 |
Koji Morita
Mamoru Suzuki
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