Title:
IMAGE PROCESSING UNIT
Document Type and Number:
Japanese Patent JP3720268
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an image processing unit that can reduce the image processing time and the cost even when receiving original image data having number of pixels in excess of a capacity of a line memory.
SOLUTION: An image division means 14a of an RPU(real time processing unit) 14 divides original image data into division image data A1 (number of horizontal pixels 2048) and A2 (number of horizontal pixels 1024). A single pixel processing means 14b and a plurality of pixel processing means 14c continuously apply processing to the division image data A1 and the processed data are transferred to a buffer 26a, where the data are stored. The single pixel processing means 14b applies processing to the division image data A2 and the processed data are transferred to a buffer 26b, where the data are once stored. The pixel processing means 14c reads the division image data A2a stored in the buffer 26a, applies processing and transfers the processed image to a buffer 26c, where the data are stored. An image compositing means 31 reads the division image data A1b, A2b stored in the buffers 26a, 26c and composites them.
Inventors:
Kazuya Morimoto
Takashi Matsutani
Hajime Sasaki
Takashi Matsutani
Hajime Sasaki
Application Number:
JP2001050032A
Publication Date:
November 24, 2005
Filing Date:
February 26, 2001
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
G06T1/60; G06T1/00; G06T3/00; H04N1/21; H04N1/387; H04N5/232; H04N101/00; (IPC1-7): H04N1/387; G06T1/60; G06T3/00; H04N1/21; H04N5/232
Domestic Patent References:
| JP2000236473A | ||||
| JP8154169A | ||||
| JP7306671A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita