To provide an impedance matching circuit with low loss which is made small in its insertion loss by apparently decreasing the internal resistance of a chip capacitor and a power amplifier.
The impedance matching circuit constituted on a dielectric substrate 1 is equipped with transmission lines 2 formed on the dielectric substrate 1 and a circuit 4 where chip capacitors 3 which are inserted in series between the transmission lines 2 and have the same electrostatic capacity value are connected in parallel. A low-impedance matching circuit is constituted on the input or output side of a transistor by combining low-loss impedance matching circuits mentioned above to constitute the power amplifier wherein the impedance of the transistor is matched.
NAKAYAMA MASATOSHI
HORIGUCHI KENICHI
MORI KAZUTOMI
