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Title:
INFORMATION PROCESSING APPARATUS
Document Type and Number:
Japanese Patent JP2010123133
Kind Code:
A
Abstract:

To reduce power consumption without stopping a clock signal of a device.

An information processing apparatus includes a CPU 11 and a memory 12. The apparatus also includes a clock generation unit 17 for generating a reference clock signal, a CPU clock setting unit 18 for setting a first clock frequency based on the reference clock signal in the CPU, a bus control unit 14 for controlling connection between the CPU and the memory by a second clock frequency based on the reference clock signal, and a clock control unit 19 for supplying a control signal for controlling a ratio between each of the first and second clock frequencies to the CPU clock setting unit and the bus control unit corresponding to operation of the CPU and the memory. The memory has a burst processing unit for performing burst transfer corresponding to data request from the CPU, and supplying a burst signal showing a burst transfer period to the clock control unit. The clock control unit outputs to the CPU clock setting unit, a control signal for lowering the first clock frequency furthermore than the case where the burst signal is not received, when the burst signal is received.


Inventors:
YOSHIKAWA YASUSHI
Application Number:
JP2009000294412
Publication Date:
June 03, 2010
Filing Date:
December 25, 2009
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F1/08; G06F12/08; G06F1/04; H04B1/16
Domestic Patent References:
JPH10199240A1998-07-31
JP2003242104A2003-08-29
JP2003108260A2003-04-11
JPH06266462A1994-09-22
JP2002278643A2002-09-27
JPH1185723A1999-03-30
JPH04262435A1992-09-17
JPS63311554A1988-12-20
Attorney, Agent or Firm:
Yamashita
Michio Nagai