Title:
INFORMATION PROCESSING DEVICE
Document Type and Number:
Japanese Patent JPS5694456
Kind Code:
A
Abstract:
PURPOSE:To realize a multiprocessor using the operation control device made into one chip, by performing master/slave designation of the operation control device made into one chip by the setting means provided outside this operation control device. CONSTITUTION:One-chip CPU101 which consists of the extrahigh integration- degree semiconductor element and is made into one chip is provided, and external one-package C-ROM102 is connected to CPU101, and the micro (mu) program which controls CPU101 is stored in C-ROM102. C-BUS103 as the common data communication line and addressable latch circuits 1041 and 1042 having the decode function are connected between CPU101 and the external, and plural control signals are output on a basis of the control signal from CPU101. A physical address of the amin memory of conversion table 105T is extracted on a basis of logical address segment information and so on sent from CPU101 by address conversion mechanism 105 to extend the address space of the amin memory.
Inventors:
KINOSHITA TSUNEO
SATOU FUMITAKA
YAMAZAKI ISAMU
SATOU FUMITAKA
YAMAZAKI ISAMU
Application Number:
JP17170079A
Publication Date:
July 30, 1981
Filing Date:
December 27, 1979
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F13/28; G06F3/00; G06F12/00; G06F13/00; G06F15/16; G06F15/177; (IPC1-7): G06F3/00; G06F13/00; G06F15/06; G06F15/16