Title:
INPUT OPTIMIZING FIELD EFFECT TRANSISTOR BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS56153811
Kind Code:
A
Abstract:
A field effect transistor bias circuit is presented which exhibits a low impedance for small signals and a high impedance for large signals. This circuit uses an operational amplifier to provide a temperature compensated low impedance voltage source for the gate bias which is optimal for small signal operation. In the presence of a large signal, the gate begins to draw current. This causes the operational amplifier to saturate and transforms the bias circuit into a high impedance source, which is optimal for large signal operation.
Inventors:
MAIKERU DEIBITSUDO RUUBIN
PAN TEIN HOO
PAN TEIN HOO
Application Number:
JP1030781A
Publication Date:
November 28, 1981
Filing Date:
January 28, 1981
Export Citation:
Assignee:
FORD AEROSPACE & COMMUNICATION
International Classes:
H03F1/30; H03F1/02; H03G3/30; (IPC1-7): H03F1/30
Domestic Patent References:
| JPS5036141A | 1975-04-05 | |||
| JPS5435756A | 1979-03-16 |