To provide an inspection circuit and an inspection method for a semiconductor device by which the size of a chip can be made small without lowering the inspection quality of an IC chip formed on a wafer.
One chip is formed by using two kinds of pad sizes, PAD (L1) and PAD (U1) capable of stable probing inspection and PAD (R1) and PAD (D1) of small size. Next, a scribing lane is used to connect the PAD (L2) and PAD (U3) capable of stable probing inspection for adjacent chips and the PAD (R1) and PAD (R1) and PAD (D1) of small size. Then, the PAD (L1) and PAD (U1) of an IC chip 1 to be inspected and the PAD (L2) and PAD (U3) of the adjacent chips 2 and 3 connected to the PAD (R1) and PAD (D1) by means of the scribe lane are inspected by probing.
HORIKITA KIMIKUNI