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Patent Searching and Data


Title:
INVERTER ARRANGEMENT
Document Type and Number:
Japanese Patent JP2004289984
Kind Code:
A
Abstract:

To provide an inverter controller capable of quickly slowing down for stopping with no noise or unstable operation even if a DC bus line voltage fluctuates under a regenerative braking operation.

The inverter arrangement comprises a microcomputer 9 that generates PWM signal to an inverse conversion part driving circuit 13 that drives a switching element of an inverse conversing part 3 to control a voltage and frequency, a multiplier 10 to which a detection signal of a voltage detecting circuit 5 for detecting the DC bus line voltage is inputted, and which corrects a voltage applied to a motor 4 according to the DC bas bur voltage, and a regenerative braking operation circuit 12 that consumes regenerative power at slow down. The level of a modulation signal or carrier wave signal (or voltage command) is corrected by the multiplier 10 for each of one tenth of hysteresis cycle according to the detection signal of the DC bus line voltage due to the regenerative braking operation, for the quick slow-down and stop of the motor 4.


Inventors:
AISAKA TOSHIFUMI
Application Number:
JP2003082411A
Publication Date:
October 14, 2004
Filing Date:
March 25, 2003
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H02P3/18; H02P27/06; (IPC1-7): H02P3/18; H02P7/63
Attorney, Agent or Firm:
Fumio Iwahashi
Tomoyasu Sakaguchi
Hiroki Naito