Title:
JOSEPHSON JUNCTION ELEMENT
Document Type and Number:
Japanese Patent JPS59135780
Kind Code:
A
Abstract:
PURPOSE:To prepare an integrated circuit with high yield by thinning an inter- layer insulating film determining the position and area of a Josephson junction and separately forming a thick second inter-layer insulating film covering a stepped difference section generated by a lower electrode film. CONSTITUTION:A lower electrode 2 and a first inter-layer insulating film 3 are formed to a substrate 1 in approximately 100nm. An opening section determining the area of a Josephson junction is also formed simultaneously. The insulating film 3 is thinned in order to shorten the time required for cleaning the surface of the lower electrode 2 by Ar ions in post-processes. A second inter-layer insulating film 4 in approximately 200nm is formed in order to prevent a defective insulation at the stepped difference section of the lower electrode 2. The surfce of the lower electrode exposed to the opening sectio is cleaned, a tunnel barrier layer 5 is formed, and an upper electrode 6 is formed. Accordingly, an integrated circuit containing a minute Josephson element can be prepared with high yield because conditions for Ar ion etching are relaxed.
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Inventors:
NISHINO JIYUICHI
TARUYA YOSHINOBU
TARUYA YOSHINOBU
Application Number:
JP872583A
Publication Date:
August 04, 1984
Filing Date:
January 24, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L39/22; (IPC1-7): H01L39/22
Attorney, Agent or Firm:
Akio Takahashi