Title:
LATCH CIRCUIT AND FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JP3519001
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a D type latch circuit or D type flip-flop circuit which is small in the number of element and reduced in power consumption.
SOLUTION: This circuit is provided with a P channel MOS field effect transistor 3 to which a gate and a well are connected for reading data signals to a master latch 1, an inverter 4 for inverting/holding signals read to the master latch 1, an N channel MOS field effect transistor 5 to which the gate and the well are connected for reading the signals outputted from the master latch to a slave latch 2 and the inverter 6 for inverting/holding the data signals read to the slave latch 2.
Inventors:
Yaoi, Yoshifumi
Sato, Yuichi
Sato, Yuichi
Application Number:
JP29431098A
Publication Date:
April 12, 2004
Filing Date:
October 15, 1998
Export Citation:
Assignee:
SHARP CORP
International Classes:
H03K3/356; H03K3/037; H03K19/00; (IPC1-7): H03K3/356; H03K3/037
Attorney, Agent or Firm:
山本 秀策
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