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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3057990
Kind Code:
B2
Abstract:

PURPOSE: To restrict an increase of a read access time due to a crosstalk caused by a parasitic capacity between digit lines and to realize high-speed accessing to a multi-port memory.
CONSTITUTION: A crosstalk between write/read digit lines is processed by a crosstalk deletion circuit in a block 19. While a deletion pulse CL12 is H, a digit line R1DL is kept at a grounding potential, so that charges of the read digit line R1DL are discharged to decrease the potential. Since a time constant is product of a total capacity CR1 of the R1DL and an on resistance RQ15 of an nchFETQ15, an increase of the potential resulting from the crosstalk is deleted by ΔV by selecting the RQ15. At the same time, an increase of the potential is deleted by ΔV from CR2 xRQ15 through earthing while a pulse CL22 is H. Accordingly, reading can be performed at high velocity in any cycle. Moreover, an increased amount of the potential can be suitably deleted by selecting a pulse width of the CL signal impressed to a gate between the read digit line and the ground. A multi-point memory can thus be read out at high speeds in such a simple constitution that a control signal is applied from outside to discharge the digit line.


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Inventors:
Toshi Sano
Application Number:
JP33924093A
Publication Date:
July 04, 2000
Filing Date:
December 06, 1993
Export Citation:
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Assignee:
NEC
International Classes:
G11C11/41; (IPC1-7): G11C11/41
Domestic Patent References:
JP4132085A
JP583186A
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)