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Title:
LOGIC GATE
Document Type and Number:
Japanese Patent JPH11163718
Kind Code:
A
Abstract:

To reduce the number of logic gates by taking out an output signal of the logic gates from two connection points during operation.

A connection point K1 between transistors P2 and N2 and a connection point K2 between transistors P3 and N3 are mutually connected and an output signal OUT of a logic gate is generated during operation in each of the points k1 and K2. When a 1st control signal L0 has a logic level of L and a 2nd control signal L1 has a logic level of H, an input signal IN appears as the output signal OUT in an inverted form and the logic gate operates as an inverter with regard to the input signal IN. When the first control signal L0 has the logic level of L, the result of NAND connection of the input signal IN and the 2nd control signal L1 occurs as the output signal OUT and the logic gate operates as a NAND gate. When the second control signal L1 has the logic level of H, the logic gate operates as a NOR gate.


Inventors:
JOHNSON BRET
SCHNEIDER RALF
Application Number:
JP27776898A
Publication Date:
June 18, 1999
Filing Date:
September 30, 1998
Export Citation:
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Assignee:
SIEMENS AG
International Classes:
H03K19/0948; H03K19/173; H03K19/20; (IPC1-7): H03K19/20; H03K19/0948; H03K19/173
Attorney, Agent or Firm:
Toshio Yano (3 outside)