PURPOSE: To realize the logic processing circuit with high accuracy even when a synchronization circuit and a logic circuit with high accuracy are not in use.
CONSTITUTION: A differentiating circuit 42 uses an internal clock CKi to differentiate an external clock CKo and its differentiating output Sa resets a counter 44 and a count output Sb is fed to a control circuit 46 till a succeeding differentiating output Sa is obtained and control signals Sc, Sd are generated by the count output Sb. The control signals Sc, Sd control delay adjustment means 26,28 to increase/decrease a delay of a ring oscillator 22. In this case, the delay of the ring oscillator 22 is controlled so that a ratio of the internal clock CKi with respect to the external clock CKo is constant thereby limiting an oscillating period of the ring oscillator 22 to a prescribed range.
JP2020102790 | IMAGE PROCESSING DEVICE |
JPH0567944 | SEMICONDUCTOR INTEGRATED CIRCUIT |