METHOD FOR FORMING STRAINED Si LAYER, METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR, SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR

Title:

METHOD FOR FORMING STRAINED Si LAYER, METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR, SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR

Document Type and Number:

Japanese Patent JP2002359188

Kind Code:

A

Abstract:

To provide a method for forming a strained Si layer, a method for manufacturing a field effect transistor, a semiconductor substrate and a field effect transistor in which a strained Si layer of good quality can be formed thicker than a conventional one.

The method for forming a strained Si layer 4 on an Si substrate through an SiGe buffer layer 3 comprises a step for forming the SiGe buffer layer on the Si substrate, a step for polishing the surface of the SiGe buffer layer to planarize at least cross-hatch like irregularities on the surface, and a step for epitaxially growing the strained Si layer on the planarized SiGe buffer layer directly or through other SiGe layer.

Inventors:

YAMAGUCHI KENJI
MIZUSHIMA KAZUKI
SHIONO ICHIRO

Application Number:

JP2001165690A

Publication Date:

December 13, 2002

Filing Date:

May 31, 2001

Export Citation:

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Assignee:

MITSUBISHI MATERIAL SILICON
MITSUBISHI MATERIALS CORP

International Classes:

H01L29/161; H01L21/20; H01L21/205; H01L29/78; (IPC1-7): H01L21/20; H01L21/205; H01L29/161; H01L29/78

Attorney, Agent or Firm:

Masatake Shiga (6 people outside)

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