Title:
MANUFACTURE OF MOS DEVICE
Document Type and Number:
Japanese Patent JPH09172176
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To perform high speed heat annealing after implanting dopants to form a source/drain extended portion, thereby reducing implantation damage and reducing accelerated diffusion in a subsequent low temperature process. SOLUTION: After implantation of dopants is performed, a substrate 18 is exposed to temperature about 800-1000 deg.C for about 5-45 seconds, thereby performing high speed annealing of the dopants. As a result of this annealing, the dopants are slightly diffused to form source/drain extended portions 34 and 40. After a sidewall insulator 46 is formed, dopants are implanted into an nMOS device 10 and a pMOS device 12, thus forming source/drain regions 42 and 44 which are doped at a high concentration for lowering the series resistance of the device. Thus, transient accelerated diffusion of dopants in a low temperature process subsequent to a sidewall insulator depositing process and the like may be reduced.
Inventors:
MAAKU ESU ROTSUDAA
Application Number:
JP31099096A
Publication Date:
June 30, 1997
Filing Date:
November 21, 1996
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/76; H01L21/265; H01L21/336; H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L29/78; H01L21/265; H01L21/266; H01L21/336; H01L21/76; H01L21/8238; H01L27/092
Attorney, Agent or Firm:
Akira Asamura (3 outside)
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