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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH1154724
Kind Code:
A
Abstract:

To make resistance in a diffusion layer of a semiconductor substrate small, and solve a problem caused by a step between a cell region and a logic region using a polysilicon plug.

A first and a second insulating film 9, 10 are formed on a semiconductor substrate along the shape of gate electrodes 5 formed on a cell region and a logic region. Then, contact holes 11 are formed in the first and the second insulating films 9, 10 in the cell region and, on inner walls of the contact holes 11, side walls 12 are formed from such material that may prevent the contact holes 11 from becoming a silicide. Conductive material is buried in the contact holes through the side walls 12 to form plugs 13 and then the second insulating film 10 is removed, with the plugs 13 and the first insulating film 9 being exposed. In the logic region, space side walls 14 are formed on the side walls of the gate electrodes 5 while the surface of the semiconductor substrate 1 is exposed and then a silicide layer 16 is formed on the surface of the semiconductor substrate 1. After that, a first interlayer insulating film 17 is formed on the semiconductor substrate 1 and the surface of the insulating film 17 is flattened with upper faces of the plugs 13 being exposed.


Inventors:
SAGAWA HIROFUMI
Application Number:
JP1997000211596
Publication Date:
June 16, 1989
Filing Date:
August 06, 1997
Export Citation:
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Assignee:
JAPAN STEEL WORKS LTD
International Classes:
B29C49/04; B29C49/48; B29C49/56; B29L22/00; (IPC1-7): B29C49/04; B29C49/48; B29C49/56; B29L22/00
Domestic Patent References:
JPS60239222A1985-11-28
Attorney, Agent or Firm:
船橋 國則