PURPOSE: To decrease the manufacturing cost, by forming a groove, by masking with a gate protecting film, at the center of a first conductivity type region formed by masking with a polycrystalline gate, for the purpose of providing first conductivity type regions on the opposite side of a second conductivity type region having low resistance.

CONSTITUTION: As+ ions 22 are implanted with a mask of a polycrystalline silicon gate 8 formed on a substrate through an oxide film 7. A PSG film 9 is provided and annealed, whereby the As+ implanted region form an N+ type layer 60. Resist 21 on the PSG film 9 is patterned by photoetching, and the PSG film 9 is etched by masking with this resist pattern so that the central part of the N+ type layer 60 is exposed. The layer 60 is divided into N+ type layers 6 by etching the same with a mask of the PSG film 9 and the resist 21. The PSG film 9 is over etched to expose a part of the surface of the N+ type layers 6 and the resist 22 is ashed. Thus, a metallic electrode 10 formed thereon is brought into contact with the surface of the P+ layer 5, a part of the surface of the n+ layers 6 and the side faces thereof. In this manner, the photoetching process for forming two regions can be omitted and, hence, the manufacturing cost can be decreased.